Low-Power Design of Delay-Constrained Circuits Using Dual-VT Process Technology

This paper addresses low-power circuit design for delay-constrained portions of cutting-edge ICs, in which scaled threshold voltages have made leakage power consumption a major concern. Assuming parameters for a dual-VT 0.10-μm process generation, we analyze two different circuits, using low-VT and high-VT devices, respectively, obeying an identical delay constraint. The power consumption comparison shows that counteracting leakage currents by replacing low-VT with high-VT devices may lead to a rapidly increasing total power consumption. This is caused by an increasing switching power, due to the dramatic sizing required in the high-VT circuit to make it satisfy the delay constraint.